英语翻译The FPGA and SerDes we use cost about $40,a about third of the cost for the cheapest Xilinx Virtex-II Pro series FPGA necessary for implementing a system as in [11].Using this hardware we currently achieve event rates that are about three

英语翻译The FPGA and SerDes we use cost about $40,a about third of the cost for the cheapest Xilinx Virtex-II Pro series FPGA necessary for implementing a system as in [11].Using this hardware we currently achieve event rates that are about three
英语翻译
The FPGA and SerDes we use cost about $40,a about third of the cost for the cheapest Xilinx Virtex-II Pro series FPGA necessary for implementing a system as in [11].Using this hardware we currently achieve event rates that are about three to four times faster than in [11].
Such a Serializer-Deserializer locally receives data on a parallel bus and then sends it over a serial output at a multiple of the parallel interface speed and vice versa for the serial receive path.The parallel interface is usually used for on-board,the serial for off-board communication.
•\x05In the approach described in [11],the receiver simply drops events if it is not ready to receive them.We implemented a flow-control scheme that ensures that all events reach its destination.In case the receiver is currently unable to receive an event because it does not have the necessary receive buffer space available,it can tell the sender to stop until space is available.
•\x05The FPGA package type chosen allow for in-house assembly and repair as opposed to the ball-grid-array package used in
[11].
1)\x05SerDes - TI TLK2501 / TLK3101:The SerDes we can use on our system is either the TLK2501 or the TLK3101 from Texas
Instruments.The TLK2501 supports up to 2.5Gbit/s,the TLK3101
supports up to 3.125Gbit/s,and has on-chip termination resistors.As terminating the differential traces correctly is not a trivial layout task,it is easier to achieve working PCB layouts with the TLK3101.Our system both supports the TLK2501 and the TLK3101 as an assembly option.We alsosuccessfully achieved mixed setups where TLK2501 and TLK3101 are communicating with each other at 2.5Gbit/s.
On the parallel side of the SerDes these chips have a 16bit transmit and a 16bit receive bus.They use 8bit/10bit coding and are also otherwise very similar to the Rocket IOs used in [11].With the 16bit word length and the 8bit/10bit coding the SerDes parallel interfaces run at 1/20 of the serial speed.
2)\x05Cables & Connector Pin-Out:We are using Serial ATA con¬nectors and cables to create Serial AER connections between our boards in multi-chip experimental setups.The connectors have seven pins,two differential pairs and three ground pins.With a SATA cable connecting boards A and B,we use the first differential pair of the cable to transmit serial AER data from the SerDes on A to the SerDes on B.The second differential pair is used to feed back a flow-control.
signal from the FPGA on B to the FPGA on A.
On the connector pins 2/3 are SerialAER+/-,pins 5/6 are FlowControl+/-.The remaining pins are the shielding,which we simply left unconnected on both sides,thus having a floating shield.
3)\x05AC Coupling:We decided to used AC coupled instead of the simpler DC coupled serial links.With AC coupled links there is no common ground reference over all the boards in a system.This eliminates board-to-board ground-bounce problems,and also reduces line frequency injection.

英语翻译The FPGA and SerDes we use cost about $40,a about third of the cost for the cheapest Xilinx Virtex-II Pro series FPGA necessary for implementing a system as in [11].Using this hardware we currently achieve event rates that are about three
The FPGA and SerDes we use cost about $40, about a third of the cost for the cheapest Xilinx Virtex-II Pro series FPGA necessary for implementing a system as in [11]. Using this hardware we currently achieve event rates that are about three to four times faster than in [11].
Such a Serializer-Deserializer locally receives data on a parallel bus and then sends it over a serial output at a multiple of the parallel interface speed and vice versa for the serial receive path. The parallel interface is usually used for on-board, the serial for off-board communication.
我们所用的FPGA和串并转换器（SerDes）只花了四十元,而执行[11] 里所述的系统中不可或缺的Xilinx Virtex-II Pro 系列 FPGA,最便宜的也要三倍于这个价钱.目前通过使用这个硬件,我们实现的事件率比起[11] 所表述的系统较快三至四倍.
这种串并转换器在本机接收由并行总线传输过来的数据,然后通过串行输出口以多倍于并行接口的速度传送出去；而在串行的接收路径反之亦然.通常并行接口是用于机载通信,而串行接口用于机外通信.
• In the approach described in [11], the receiver simply drops events if it is not ready to receive them. We implemented a flow-control scheme that ensures that all events reach its destination. In case the receiver is currently unable to receive an event because it does not have the necessary receive buffer space available, it can tell the sender to stop until space is available.
• The FPGA package type chosen allow for in-house assembly and repair as opposed to the ball-grid-array package used in
在[11]里所阐述的方法,如果接收器还未准备接收事件数据,它会直接就删除事件.我们执行一个信息流控制设计以确保所有的事件都到达目的地.若是接收器因为没有必要的接收缓冲空间导致目前不能接收事件,它可以通知发送者停止发送直到可用空间的出现.
选择这类FPGA封装可以进行内部组装与维修,相反于下列组件所使用的球栅阵列封装：
[11].
1)SerDes - TI TLK2501 / TLK3101: The SerDes we can use on our system is either the TLK2501 or the TLK3101 from Texas Instruments. The TLK2501 supports up to 2.5Gbit/s, the TLK3101 supports up to 3.125Gbit/s, and has on-chip termination resistors. As terminating the differential traces correctly is not a trivial layout task, it is easier to achieve working PCB layouts with the TLK3101. Our system both supports the TLK2501 and the TLK3101 as an assembly option. We also successfully achieved mixed setups where TLK2501 and TLK3101 are communicating with each other at 2.5Gbit/s.
On the parallel side of the SerDes these chips have a 16bit transmit and a 16bit receive bus. They use 8bit/10bit coding and are also otherwise very similar to the Rocket IOs used in [11]. With the 16bit word length and the 8bit/10bit coding the SerDes parallel interfaces run at 1/20 of the serial speed.
[11].
1. SerDes -TI TLK2501 / TLK3101：可以在我们系统使用的SerDes是德克萨斯仪器公司生产的TLK2501 或TLK3101.TLK2501可支持高达2.5Gbit/s带宽,the TLK3101则可达3.125Gbit/s,且还有片内终止电阻.由于正确终止差分示踪不是个平常的版面工作,比较容易实现是对TLK3101进行PCB版图操作.我们的系统都支持TLK2501和TLK3101这两个组装选择.我们也成功把TLK2501和TLK3101组合,互相以2.5Gbit/s通信.
在SerDes的并行一边,这些芯片都有个16位输出和16位接收总线.它们用8/10位编码,其他方面也与 [11]系统中使用的Rocket收发器相同.以16位码字长度和8/10位编码的配置,SerDes并行接口的运行速度只有串行接口的1/20.
2) Cables & Connector Pin-Out: We are using Serial ATA connectors and cables to create Serial AER connections between our boards in multi-chip experimental setups. The connectors have seven pins, two differential pairs and three ground pins. With a SATA cable connecting boards A and B, we use the first differential pair of the cable to transmit serial AER data from the SerDes on A to the SerDes on B. The second differential pair is used to feed back a flow-control signal from the FPGA on B to the FPGA on A.
On the connector pins 2/3 are SerialAER+/-, pins 5/6 are FlowControl+/-. The remaining pins are the shielding, which we simply left unconnected on both sides, thus having a floating shield.
2. 线缆与连接器引出线：我们多芯片实验设备的板与板之间的串行连接是使用串行ATA连接器与线缆来实现.该连接器共有七根线,两对差分线和三根地线.通过一条SATA线缆将A板与B板连接,我们利用线缆的第一个对差分线从A板上的SerDes将串行AER数据传送到B板上的SerDes.另一对差分线是用于把信息流控制信号从B板的FPGA反馈回A板上的FPGA.
连接器的第2/3线是串行AER+/-,第5/6线是信息流控制+/-.剩余的线作为屏蔽,两边都留着不连接,形成一个悬浮屏蔽罩.
3)AC Coupling: We decided to use AC coupled instead of the simpler DC coupled serial links. With AC coupled links there is no common ground reference over all the boards in a system. This eliminates board-to-board ground-bounce problems, and also reduces line frequency injection.
3. AC 耦合：我们决定用AC耦合链路而不是较简单的DC耦合链路.用AC耦合链路能使系统中的所有版块都没有公共接地参照.这可以消除板对板的地电压反弹问题,而且还可以减少行频注入.
【英语牛人团】

The FPGA and SerDes we use cost about $40, a about third of the cost for the cheapest Xilinx Virtex-II Pro series FPGA necessary for implementing a system as in [11].
我们使用FPGA和SerDes花费了40美元,大约三分之...

全部展开

The FPGA and SerDes we use cost about $40, a about third of the cost for the cheapest Xilinx Virtex-II Pro series FPGA necessary for implementing a system as in [11].
我们使用FPGA和SerDes花费了40美元,大约三分之一的成本便宜Virtex-II箴系列必要讲师生动FPGA来实现一个系统[11]。
Using this hardware we currently achieve event rates that are about three to four times faster than in [11].
目前我们使用这个硬件,实现事件发生率大约三到四倍于[11]。
Such a Serializer-Deserializer locally receives data on a parallel bus and then sends it over a serial output at a multiple of the parallel interface speed and vice versa for the serial receive path.
这样一个Serializer-Deserializer局部接收数据并行总线上,然后将它超过一个串行输出在多个平行界面速度,反之亦然,接受路径。系列
The parallel interface is usually used for on-board, the serial for off-board communication.
并行接口是通常用于车载、系列为沟通。严禁进行场外
•In the approach described in [11], the receiver simply drops events if it is not ready to receive them.
•在方法[11]中描述,话筒事件只是下降,如果它不是随时要接受他们。
We implemented a flow-control scheme that ensures that all events reach its destination.
我们实行了流量控制的方案,以确保所有的事件到达目的地。
In case the receiver is currently unable to receive an event because it does not have the necessary receive buffer space available, it can tell the sender to stop until space is available.
如果接收器是目前无法接受一个事件,因为它没有必要的接收缓冲区的可用空间,它就会告诉发件人停止,除非空间是可用的。
•The FPGA package type chosen allow for in-house assembly and repair as opposed to the ball-grid-array package used in
•FPGA包装类型选择允许内部组装与维护与ball-grid-array包装用于
[11].
[11]。
1)SerDes - TI TLK2501 / TLK3101: The SerDes we can use on our system is either the TLK2501 or the TLK3101 from Texas
1)SerDes -钛TLK2501 / TLK3101:SerDes我们可以用在我们的系统里,无论是从德州TLK3101 TLK2501或
Instruments.
仪器。
The TLK2501 supports up to 2.5Gbit/s, the TLK3101
TLK2501高达2.5的支持Gbit / s,TLK3101
supports up to 3.125Gbit/s, and has on-chip termination resistors.
支持多达3.125 Gbit / s,单片终端电阻。
As terminating the differential traces correctly is not a trivial layout task, it is easier to achieve working PCB layouts with the TLK3101.
作为终止微分痕迹不是一个微不足道的正确布置的任务,但它更容易实现的TLK3101 PCB布局和工作。
Our system both supports the TLK2501 and the TLK3101 as an assembly option.
我们的系统都TLK3101 TLK2501和支持其装配成的选择。
We alsosuccessfully achieved mixed setups where TLK2501 and TLK3101 are communicating with each other at 2.5Gbit/s.
我们alsosuccessfully取得的地方,TLK3101设置TLK2501和彼此之间的沟通是2.5 Gbit /秒。
On the parallel side of the SerDes these chips have a 16bit transmit and a 16bit receive bus.
在平行边的SerDes这些芯片是一种16位传送和一种16位接受公共汽车。
They use 8bit/10bit coding and are also otherwise very similar to the Rocket IOs used in [11].
他们使用8位/ 10位编码,否则会很类似于火箭网路作业系统用于[11]。
With the 16bit word length and the 8bit/10bit coding the SerDes parallel interfaces run at 1/20 of the serial speed.
与16位字长和8位/ 10位并行接口编码的SerDes运行在1/20的串行速度。
2)Cables & Connector Pin-Out: We
2)电缆和连接器线图:我们

收起

我们使用FPGA和SerDes花费了40美元,大约三分之一的成本便宜Virtex-II箴系列必要讲师生动FPGA来实现一个系统[11]。目前我们使用这个硬件,实现事件发生率大约三到四倍于[11]。
这样一个Serializer-Deserializer局部接收数据并行总线上,然后将它超过一个串行输出在多个平行界面速度,反之亦然,接受路径。系列并行接口是通常用于车载、系列为沟通。严禁进行场外...

全部展开

我们使用FPGA和SerDes花费了40美元,大约三分之一的成本便宜Virtex-II箴系列必要讲师生动FPGA来实现一个系统[11]。目前我们使用这个硬件,实现事件发生率大约三到四倍于[11]。
这样一个Serializer-Deserializer局部接收数据并行总线上,然后将它超过一个串行输出在多个平行界面速度,反之亦然,接受路径。系列并行接口是通常用于车载、系列为沟通。严禁进行场外
•在方法[11]中描述,话筒事件只是下降,如果它不是随时要接受他们。我们实行了流量控制的方案,以确保所有的事件到达目的地。如果接收器是目前无法接受一个事件,因为它没有必要的接收缓冲区的可用空间,它就会告诉发件人停止,除非空间是可用的。
•FPGA包装类型选择允许内部组装与维护与ball-grid-array包装用于
[11]。
1)SerDes -钛TLK2501 / TLK3101:SerDes我们可以用在我们的系统里,无论是从德州TLK3101 TLK2501或
仪器。TLK2501高达2.5的支持Gbit / s,TLK3101
支持多达3.125 Gbit / s,单片终端电阻。作为终止微分痕迹不是一个微不足道的正确布置的任务,但它更容易实现的TLK3101 PCB布局和工作。我们的系统都TLK3101 TLK2501和支持其装配成的选择。我们alsosuccessfully取得的地方,TLK3101设置TLK2501和彼此之间的沟通是2.5 Gbit /秒。
在平行边的SerDes这些芯片是一种16位传送和一种16位接受公共汽车。他们使用8位/ 10位编码,否则会很类似于火箭网路作业系统用于[11]。与16位字长和8位/ 10位并行接口编码的SerDes运行在1/20的串行速度。
2)电缆和连接器线图:我们使用串行ATA¬nectors欺诈和电缆连接串行正在创造我们multi-chip板实验装备上。连接器有七针、两个微分对子和三个地面针。与一个SATA电缆连接板a和B,我们使用第一微分对电缆传输的数据序列正在SerDes在对SerDes在2第二微分一对是用来饲养回流量控制的。
信号从FPGA在FPGA上B。
在插脚SerialAER 2/3是+ / -、别针5/6的FlowControl + / -。剩下的销屏蔽,我们不只是离开两边,因此在一个浮动的盾牌。
3)交流耦合:我们决定使用而不是交流耦合相对简单的直流耦合串行链路。与AC耦合环节没有共同点参考全板系统。这就消除了围绕着板对板ground-bounce问题,同时减少电源频率注射液的热原检查。

收起